Vertical CMOS Inverter With LTPO Technology for Circuit Applications in Active-Matrix Display

A CMOS inverter using low-temperature polycrystalline silicon and oxide thin-film transistors (LTPO TFTs) with 3-D structure was proposed for narrow-bezel and high-resolution active-matrix organic light-emitting diode (AMOLED) display. To reduce the bezel area, an n-type indium-gallium-zinc oxide (IGZO) TFT was fabricated in the vertically aligned same position on a p-type low-temperature polycrystalline silicon (LTPS) TFT without additional photograph mask and process compared to conventional planar CMOS inverter. As a result, the effective circuit area was drastically reduced from 1581 to 775 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup>. Since the IGZO TFT and LTPS TFT shared one gate electrode in the vertical CMOS inverter, the IGZO TFT has a dual gate structure leading to the enhancement of the electrical performance and stability of the IGZO TFT. Thus, the linear mobility of the IGZO TFT in the vertical CMOS inverter was improved from 5.55 to 7.75 cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup>/Vs and the voltage gain of the vertical CMOS inverter was improved from 112.95 to 140.20 V/V compared to that in the planar inverter. Furthermore, the positive bias stress (PBS) stability of the vertical CMOS inverter was improved, resulting in the decrease of voltage transfer curve (VTC) shift from 0.63 to 0.25 V after applying a positive unipolar pulse with a pulsewidth of 20 μs and pulse amplitude of 5 V at <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>DD</roman></sub> = 5 V and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>SS</roman></sub> = 0 V.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2025-05-06
DOI
https://doi.org/10.1109/ted.2025.3564565
Citations
3
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
2.19

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article

Vertical CMOS Inverter With LTPO Technology for Circuit Applications in Active-Matrix Display

Hyun Jae Kim, I. Sak Lee, Juhn S. Yoo, Jung Chul Kim et al.
3 citations
IEEE Transactions on Electron Devices
3D IC and TSV technologies
2.19
article

Vertical CMOS Inverter With LTPO Technology for Circuit Applications in Active-Matrix Display

Hyun Jae Kim, I. Sak Lee, Juhn S. Yoo, Jung Chul Kim, Hyun Chul Choi, Hyung Tae Kim, Dong Keun Lee
article en
3 citations

Abstract

A CMOS inverter using low-temperature polycrystalline silicon and oxide thin-film transistors (LTPO TFTs) with 3-D structure was proposed for narrow-bezel and high-resolution active-matrix organic light-emitting diode (AMOLED) display. To reduce the bezel area, an n-type indium-gallium-zinc oxide (IGZO) TFT was fabricated in the vertically aligned same position on a p-type low-temperature polycrystalline silicon (LTPS) TFT without additional photograph mask and process compared to conventional planar CMOS inverter. As a result, the effective circuit area was drastically reduced from 1581 to 775 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup>. Since the IGZO TFT and LTPS TFT shared one gate electrode in the vertical CMOS inverter, the IGZO TFT has a dual gate structure leading to the enhancement of the electrical performance and stability of the IGZO TFT. Thus, the linear mobility of the IGZO TFT in the vertical CMOS inverter was improved from 5.55 to 7.75 cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup>/Vs and the voltage gain of the vertical CMOS inverter was improved from 112.95 to 140.20 V/V compared to that in the planar inverter. Furthermore, the positive bias stress (PBS) stability of the vertical CMOS inverter was improved, resulting in the decrease of voltage transfer curve (VTC) shift from 0.63 to 0.25 V after applying a positive unipolar pulse with a pulsewidth of 20 μs and pulse amplitude of 5 V at <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>DD</roman></sub> = 5 V and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>SS</roman></sub> = 0 V.

IEEE Transactions on Electron DevicesVol. 72(6)
Yonsei University (KR), LG (South Korea) (KR)
LG Display
Affordable and clean energy
Openalex Percentile: Top 12%
3D IC and TSV technologies
2.19
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