A 4.447 mW at 100 MHz and 49.62% Uniqueness XNOR–XOR RO PUF ASIC Using 180-nm CMOS Process for IoT Security Applications

Physical unclonable functions (PUFs) are increasingly recognized as a key technology for enhancing hardware and the Internet of Things (IoT) security. The IoT devices are often plagued by weak security measures, making them susceptible to various external threats. To address these vulnerabilities, robust and reliable security solutions are critical. This study introduces a highly reliable and low-power PUF application-specific integrated circuit (ASIC) design specifically designed for the IoT security applications. Initially, the proposed design is deployed on a Xilinx ZYNQ 7000 field-programmable gate array (FPGA) board operating at 100 MHz and later designed and fabricated using the Cadence Innovus in the 180-nm CMOS process on silicon. This work presents and evaluates a novel <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xnor</small>–<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xor</small> ring oscillator (RO) PUF with a configurable frequency. The design’s performance is analyzed using statistical metrics, including reliability, uniqueness, and uniformity. The <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xnor</small>–<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xor</small> RO PUF ASIC demonstrates max reliability of 91.92%, a uniqueness of 49.62%, and a uniformity of 50.19% on silicon.