Analysis and Optimization of Nanosheet FETs With Vertically Nonuniform Source/Drain Etch Profiles

The effects of the nonuniform source/drain (S/D) etch profiles on the electrical characteristics of vertically stacked nanosheet field-effect transistors (NSFETs) were investigated. A vertically nonuniform S/D profile leads to a 13% larger <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> delay than an ideal uniform one. It is shown that the inter-NS channel length differences are a primary contributor to performance degradation in the case of the nonuniform S/D profile. Device and process parameters are optimized to mitigate the degradation, such as NS thicknesses (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>NS</roman></sub>’s) of each layer and punchthrough stopper (PTS) doping concentrations. These optimizations effectively restore the initial degradation from 13% to 3%.