Reconfigurable 9T Static RAM Design With Dynamic Switching Between Content-Addressable Memory and In-Memory Computing

Most modern computers are based on a von Neumann architecture, in which computational data are moved between processors and memory. However, due to the gap in operation speed between the processor and memory, this architecture has poor energy efficiency and suboptimal performance, a phenomenon termed the von Neumann bottleneck. In-memory computing (IMC) is a promising architecture for solving the problem of the von Neumann bottleneck. IMC reduces data transmission by performing operations in memory to increase energy efficiency and throughput. This paper proposes a type of reconfigurable 9T static random-access memory (SRAM) with a novel dynamic switching technique, called DST-SRAM. By using the dynamic switching technique, DST-SRAM can be reconfigured into content-addressable memory (CAM), SRAM, and IMC structures as needed. A single-ended write circuit is used to reduce write power dissipation. By using Taiwan Semiconductor Manufacturing Company 40-nm technology, 256 × 64 DST-SRAM was implemented to verify its feasibility in evaluation experiments, and the power delay product of DST-SRAM was up to 56% lower than those of two state-of-the-art reconfigurable SRAM architectures.