High-Level Synthesis-Based Forensic Watermarking of Hardware IPs Using IP Vendor’s DNA Signature

The threats of hardware intellectual property (IP) piracy and fraud IP ownership claim pose a grave concern for the hardware security community. This paper proposes a novel high-level synthesis (HLS) methodology that exploits IP vendor’s deoxyribonucleic acid (DNA) signature to form a forensic hardware watermark for covertly embedding into allocation phase of the design synthesis process. The forensic watermark signature is generated by extracting unique DNA components such as microsatellites and fragments. The proposed approach, when compared with the existing HLS watermarking techniques, revealed enhancement in security in terms of probability of coincidence and tamper tolerance, at nominal design overhead.

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Publication Details

Journal
IEEE Embedded Systems Letters
Published
2025-05-05
DOI
https://doi.org/10.1109/les.2025.3566674
Primary Topic
Physical Unclonable Functions (PUFs) and Hardware Security
Type
article
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article

High-Level Synthesis-Based Forensic Watermarking of Hardware IPs Using IP Vendor’s DNA Signature

Anirban Sengupta, Aditya Anshul, Nabendu Bhui
IEEE Embedded Systems Letters
Physical Unclonable Functions (PUFs) and Hardware Security
article

High-Level Synthesis-Based Forensic Watermarking of Hardware IPs Using IP Vendor’s DNA Signature

Anirban Sengupta, Aditya Anshul, Nabendu Bhui
article en

Abstract

The threats of hardware intellectual property (IP) piracy and fraud IP ownership claim pose a grave concern for the hardware security community. This paper proposes a novel high-level synthesis (HLS) methodology that exploits IP vendor’s deoxyribonucleic acid (DNA) signature to form a forensic hardware watermark for covertly embedding into allocation phase of the design synthesis process. The forensic watermark signature is generated by extracting unique DNA components such as microsatellites and fragments. The proposed approach, when compared with the existing HLS watermarking techniques, revealed enhancement in security in terms of probability of coincidence and tamper tolerance, at nominal design overhead.

IEEE Embedded Systems LettersVol. 18(1)
Indian Institute of Technology Indore (IN)
Openalex Percentile: Top 92%
Physical Unclonable Functions (PUFs) and Hardware Security
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High-Level Synthesis-Based Forensic Watermarking of Hardware IPs Using IP Vendor’s DNA Signature — Anirban Sengupta, Aditya Anshul, et al. · IEEE Embedded Systems Letters (2025) | TGRS Research Map | TGRS