Power Efficient Multiplier Design for Error Resilient Edge Applications

Edge devices require low-power and efficient hardware to support data-intensive computations in real-time applications. Traditional multipliers are computationally demanding and consume considerable power, however, approximate circuits are used in applications requiring low power consumption and high performance. The approximate multiplier is the key arithmetic function in many error-tolerant applications such as signal processing, image processing, etc. This letter presents a powerefficient approximate multiplier design tailored for error-resilient applications on edge devices. The proposed design employs an approximate 4:2 compressor based on input reordering. Input reordering is used to reduce the number of combinations which leads to low power consumption. The experimental analysis demonstrates the efficacy of the proposed approximate multiplier that achieves power and area savings. The results highlight the viability of DNN workloads in resource-constrained environments and the potential for extending edge device lifespans without compromising the accuracy required for real-time, error-tolerant tasks.