Synaptic Weight Cell Enabled by Ferroelectric FETs With Gate Side Charge Injection

The ferroelectric field-effect transistor (FeFET) has been extensively studied as a synaptic weight cell due to its ability to tune conductance states via partial polarization switching, along with its energy efficiency and scalability. However, a significant challenge arises from the need for pulse amplitude modulation to achieve acceptable performance, which greatly complicates the peripheral circuitry. To address this issue, this paper proposes utilizing an FeFET with gate-side charge injection by incorporating a charge trap layer (CTL), such as SiN<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub>, between the gate metal and the ferroelectric layer. This approach not only enhances the FeFET’s memory window, making it favorable for vertical NAND applications, but also increases the number of available <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> states through charge trapping in the CTL. Experimental results demonstrate the effectiveness of our design, showing substantial improvements over conventional FeFETs in both the number of intermediate states and the linearity of conductance tuning under identical pulse train, positioning it as a promising candidate for synaptic weight cells.