Development of an inspection method for electrical leakage tailored to target defect

As semiconductor performance design patterns advance, internal electrical defects more have attracted interest rather than surface defects. Consequently, in-line Voltage Contrast (VC) inspection utilizing Scanning Electron Microscopy (SEM) plays pivotal role to detect the flow of electrons in internal circuit. Nevertheless, VC inspection faces challenges including inadequate coverage and the charging effect, which diminishes detection capability by accumulating electrons in nearby internal structure. Specifically, it poses a significant obstacle in detecting gate leakage and abnormal current leakage in NMOS, representing device characteristics and potentially leading to malfunction. This paper proposes using Point Vector Scanning (PVS), which targets specific points instead of scanning the entire surface. This paper introduces a facility operation method optimized for target defects that can maximize productivity using PVS. In addition, the charging effect, which is a disadvantage of the existing RS, has been improved, and the higher BVC detection ability has been confirmed through failure analysis in high volume manufacturing. Additionally, by analyzing gray levels characterized by specific patterns and device characteristics, we suggests the potential for becoming a pivotal method for quantifying electrical characteristics under GAA manufacturing process.