Critical in-line OCD metrology for CFET manufacturing

As semiconductor technology advances, scaling transistors becomes increasingly challenging. The difficulty in defining and scaling devices is compounded by short channel effects, parasitic effects, and metal resistance, which limit gate-length scaling, device density, and metal pitch. Consequently, the complementary FET (CFET) architecture offers a solution by vertically stacking nFET and pFET transistors, thereby overcoming the limitations of n-to-p separation. This 'folding' approach reduces the cell active area footprint, making CFET a promising candidate for next-generation semiconductor nodes. However, CFET adoption introduces complexities in manufacturing and process control. Tight control is needed for the Si/SiGe superlattices with multiple layers and different Ge content, both for the CFET performance and the novel middle-dielectric- insulation (MDI) process. A higher aspect ratio is used in all front-end patterning applications. The multiple novels etch-back steps require tight vertical edge placement error (vEPE). Inner spacer uniformity control also becomes more challenging. In-line Optical Critical Dimension (OCD) is essential to control all the complex processes involved in complementary FET (CFET) manufacturing, enabling fast, non-destructive, and precise tracking of all critical parameters, enabling reduction of the wafer-to-wafer and within-the-wafer variations. The current paper presents OCD monitoring results for the development of the essential CFET process steps, starting from the superlattice formation down to the inner spacer (ISP) etch back. The required robust OCD models were created for all process steps based on the specially designed splits defining process windows, validated with the reference metrology, and applied to the pilot line process control.