I4C... Improving I2C’s Dynamism and Efficiency

I2C is a popular interconnect bus for integrated circuits that employs an open-drain design to support multiple controllers. Originally designed for television motherboards with a static configuration of chips, I2C is now used in nearly every corner of electronics, from wearables to phones to satellites. Some emerging applications, however, are more dynamic and distributed than I2C can support today, limiting its utility. In particular, one typically static, design-time parameter---the value of a pull-up resistor---is chosen to roughly match the total distributed bus and gate capacitance, ensuring a pull-up rise time that satisfies the I2C spec. But with greater dynamism---when many I2C nodes are added or removed at run-time---a static pull-up resistor can lead to a bus that is at best inefficient and at worst inoperable. In this paper, we present a system that can measure the rise time in situ and at I2C data rates, allowing us to optimally adjust the pull-up resistor at runtime. With this rise time measurement capability in hand, we show how it can be used for other useful and novel functions, including detecting when I2C nodes are added or removed, enabling an efficient inband-interrupt signaling scheme that eliminates the need for interrupt polling, and even full-duplex reverse data transfer encoded into clock edges. We implement our design, called I4C, using commercial microcontrollers and discrete electronics, and evaluate it on a testbed of several nodes, demonstrating its viability and efficiency.