T-gate with dual dielectric layer for p-GaN/AlGaN/GaN HFETs: Suppressed gate leakage current and increased gate voltage range
• Proposed a novel T-shaped gate with a dual dielectric layer (Al 2 O 3 /SiO 2 ) for E-mode p-GaN/AlGaN/GaN HFETs. • Selective dual-insulator placement at the gate edge suppresses leakage while maintaining a Schottky contact in the inner gate region. • Enabled hole injection and extended gate voltage swing, overcoming the limitations of conventional p-GaN gate HFETs. • Demonstrated the feasibility of the dual dielectric structure for enhancing device performance and reliability in GaN power applications. • Significantly reduced gate leakage current (∼10 −7 A/mm at V GS = 8 V) compared to conventional structures (∼10 −3 A/mm). • Improved gate forward breakdown voltage to 16 V, doubling the conventional value of 8.5 V. • Enhanced off-state breakdown voltage, demonstrating improved high-voltage operation reliability. In this paper, a T-shaped gate with a dual dielectric layer is proposed for enhancement-mode p-GaN/AlGaN/GaN heterojunction field-effect transistors (HFETs), designed to reduce gate leakage current and improve gate forward breakdown voltage. The proposed dual dielectric layer, comprising Al 2 O 3 and SiO 2 films, modulates the energy band structure at the gate edge to suppress the hole injection from the gate metal to the p-GaN layer. As a result, the p-GaN/AlGaN/GaN HFET with the proposed T-shaped gate demonstrated a significantly reduced gate leakage current of ∼ 10 -7 A/mm at V GS = 8 V and a substantially higher gate forward breakdown voltage of 16 V, compared to a conventional structure with a gate leakage current of ∼ 10 -3 A/mm at V GS = 8 V and a gate forward breakdown voltage of 8.5 V. Additionally, the off-state breakdown voltage of the proposed device was noticeably improved. These results suggest that the proposed dual dielectric configuration offers a promising approach to overcoming the limited gate voltage range of conventional p-GaN/AlGaN/GaN HFETs, thereby enhancing device reliability.
Authors
- G. Atmaca (ORCID: https://orcid.org/0000-0002-8138-6632)
- Ho‐Young Cha (ORCID: https://orcid.org/0000-0002-1363-3152)
- Min‐Gi Jeong (ORCID: https://orcid.org/0000-0003-4650-7790)
Institutions
- NOK Corporation (Japan) (JP)
- Hongik University (KR)
Publication Details
- Journal
- Results in Physics
- Published
- 2025-05-04
- DOI
- https://doi.org/10.1016/j.rinp.2025.108294
- Citations
- 2
- Primary Topic
- GaN-based semiconductor devices and materials
- Type
- article
- Field-Weighted Citation Impact
- 2.52