Impacts of Device Geometry and Layout on Temperature Profile during Large‐Area Photonic Curing

Photonic curing is a large‐area, high‐throughput thermal processing technique that uses high‐intensity pulsed light to selectively cure thin films on thermally sensitive substrates. This study employs 3‐dimensional (3D) simulation to show, for the first time, that gate geometry significantly impacts peak curing temperature during photonic curing. The simulation results are experimentally validated by photonically curing solution‐processed indium zinc oxide for thin‐film transistors with different bottom gate geometries and comparing their performance to thermally annealed control devices. Under the same photonic curing pulse, for a fixed aspect ratio, peak photonic curing temperature increases with larger gate area, while for a fixed area, peak photonic curing temperature decreases with increasing aspect ratio. For different gate areas and aspect ratios, the simulated peak photonic curing temperature varies from ≈200 to 450 °C, which strongly impacts metal‐hydroxide to metal‐oxide conversion in sol–gels. Thus, the subsequent transistor performance is strongly influenced by the gate geometry. For example, for increasing gate area with fixed aspect ratio of 1, the average mobility increases from 1.61 to 12.52 cm 2 V −1 s −1 , while the threshold voltage decreases from 2.14 to −5.68 V. Thus, this study provides valuable insights for adopting 3D simulation to design transistors for complex large‐area electronics using photonic curing.