Investigation of Hardware Implementation of a Feedforward Neural Network for Handwritten Digit Recognition Based on FPGA

A hardware implementation based on Field Programmable Gate Array (FPGA) of a single-layer feedforward neural network for handwritten digit recognition has been developed. The effect of the network coefficient bit depth on the recognition accuracy and FPGA hardware costs has been studied. The neural network was trained using the MNIST handwritten digit database. The neural network prototype was implemented as an IP core on the ZYBO Z7 debug board. The developed prototype was used to perform experiments with different bit depths of neural network coefficient representation. Graphs of recognition accuracy and the amount of FPGA hardware resources depending on the bit depth of neural network coefficient representation have been constructed. The coefficients obtained as a result of neural network training have been analyzed using decomposition into bit planes. It has been shown that 5 bits are sufficient to represent neural network coefficients, since they contain the main information learned by the network, ensuring economical use of FPGA resources and high recognition accuracy (92.4 %).