Memristor loaded cross-coupled differential voltage sense amplifier design with improved performance

Sense amplifiers have of late become an important class of circuits due the major role they play in the design of low voltage memory design. It is an active circuit capable to enhance signal promulgation from the selected cell in a memory array to peripheral logic circuits and changes the random logic levels on a bit-line to the digital logic levels of the Boolean circuits in the periphery. In this paper the memristor loaded cross-coupled differential voltage sense amplifier is proposed as a possible surrogate for CMOS based cross coupled differential amplifier to reduce the area size, increase the gain and the speed of operation. With the exponential increase in the memory array sizes the bit line capacitance and cell-access resistance has become very large and this merger conjoined with the further reduction in output energy produced by the cell during reading will aggregate in the generation of a small signals from each selected cell. These small signals will make it difficult for data value detection and determination and will cause a prolonged latency times. To enhance performance speed and to provide signals that can be properly read as logic 0/1 many sense amplifiers have been designed to give faster sensing by responding to low voltage swings. To improve the gain of the sense amplifier by increasing the load resistance the memristor cells is in cooperated in amplifier. The memristor was selected as it propound reduced leakage current, populate less space area and because of quantization of conductance using memristive state allows for easy adjustability of the sense amplifier. The proposed memristor loaded sense amplifier was compared to the conventional CMOS based cross-coupled sense amplifier.