High-Storage, Low-Variability, and Low-Power Read-After-Write Superlattice HfO<sub>2</sub>/ZrO<sub>2</sub> FeFET Memory Device by Using a Multifunctional MoO<sub>x</sub>/TiON Layer

In this study, we present a multifunctional gate oxide ferroelectric transistor technology fully compatible with existing commercial semiconductor devices. In contrast to single electrodes, this electrode employs a TiN/Mo (30 nm)/barrier layer of TiN (BL-TiN) (2.5 nm), with an insulator composed of an angstrom-laminated HfO2/ZrO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub> structure, featuring each layer of 6.5 Å thickness. Based on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>it</roman></sub> and x-ray photoelectron (XPS) results, the inclusion of MoO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>/TiO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>y</i></sub> layer highly suppresses trapping charges and leakage current of metal-ferroelectric-insulator-semiconductor (MFIS)-ferroelectric field-effect transistor (FeFET). The substantial defect reduction enables low-voltage immediate read-after-write and significantly enhances erase (ER) and program (PG) speeds by 61% and 43%, respectively. Furthermore, SEM and grazing incidence X-ray diffraction (GIXRD) analyses confirm the formation of smaller HZO grains on this layer, which enhances polarization switching uniformity, enables high storage density with 3 bits/cell triple-level cell (TLC) operation, minimizes device-to-device (DtD) variability, and achieves exceptional endurance exceeding 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>9</roman></sup> cycles. Notably, the low-interface-defect and mass-ordered HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub>/ZrO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub> structure has been demonstrated to effectively enhance thermal stability, and achieved a ten-year retention at 108.9 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C, exceeding the current industrial dynamic random access memory (DRAM) standard of 95 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C. This technology establishes a foundation for the application in future neuromorphic network designs.

Authors

Institutions

Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2025-05-02
DOI
https://doi.org/10.1109/ted.2025.3560272
Citations
1
Primary Topic
Ferroelectric and Negative Capacitance Devices
Type
article
Field-Weighted Citation Impact
0.73
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

High-Storage, Low-Variability, and Low-Power Read-After-Write Superlattice HfO2/ZrO2 FeFET Memory Device by Using a Multifunctional MoOx/TiON Layer

Y. S. Tasi, Ying–Tsan Tang, Zheng-Kai Chen, Zi-Rong Huang et al.
1 citations
IEEE Transactions on Electron Devices
Ferroelectric and Negative Capacitance Devices
0.73
article

High-Storage, Low-Variability, and Low-Power Read-After-Write Superlattice HfO2/ZrO2 FeFET Memory Device by Using a Multifunctional MoOx/TiON Layer

Y. S. Tasi, Ying–Tsan Tang, Zheng-Kai Chen, Zi-Rong Huang, Ming-Wei Hsiung, Yuting Chen, Cheng-Rui Liu, C. S. Pai, Sheng-Min Wang
article en
1 citations

Abstract

In this study, we present a multifunctional gate oxide ferroelectric transistor technology fully compatible with existing commercial semiconductor devices. In contrast to single electrodes, this electrode employs a TiN/Mo (30 nm)/barrier layer of TiN (BL-TiN) (2.5 nm), with an insulator composed of an angstrom-laminated HfO2/ZrO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub> structure, featuring each layer of 6.5 Å thickness. Based on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>it</roman></sub> and x-ray photoelectron (XPS) results, the inclusion of MoO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>/TiO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>y</i></sub> layer highly suppresses trapping charges and leakage current of metal-ferroelectric-insulator-semiconductor (MFIS)-ferroelectric field-effect transistor (FeFET). The substantial defect reduction enables low-voltage immediate read-after-write and significantly enhances erase (ER) and program (PG) speeds by 61% and 43%, respectively. Furthermore, SEM and grazing incidence X-ray diffraction (GIXRD) analyses confirm the formation of smaller HZO grains on this layer, which enhances polarization switching uniformity, enables high storage density with 3 bits/cell triple-level cell (TLC) operation, minimizes device-to-device (DtD) variability, and achieves exceptional endurance exceeding 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>9</roman></sup> cycles. Notably, the low-interface-defect and mass-ordered HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub>/ZrO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub> structure has been demonstrated to effectively enhance thermal stability, and achieved a ten-year retention at 108.9 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C, exceeding the current industrial dynamic random access memory (DRAM) standard of 95 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C. This technology establishes a foundation for the application in future neuromorphic network designs.

IEEE Transactions on Electron DevicesVol. 72(6)
National Central University (TW)
Affordable and clean energy
Openalex Percentile: Top 29%
Ferroelectric and Negative Capacitance Devices
0.73
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.