SSA: An Effective Secure Scan Architecture Based on Hidden, Randomly Inserted Keys and PUF

With the rapid growth of Internet of Things (IoT) applications, ensuring the data privacy and security has become a critical concern. The security of integrated circuits (ICs) in IoT systems is of paramount importance. As IC integration increases, circuit testing becomes increasingly challenging. Design For Testability (DFT) techniques improve testability, but scan-based methods can be easily exploited by unauthorized users to steal confidential information. For this reason, researchers have proposed various defense techniques, but each technique has its limitations. In order to effectively protect the scan chains of ICs from illegal access, this paper presents a novel DFT framework based on hidden, randomly inserted key seeds and Physical Unclonable Function (PUF). A multiple-input shift register is used as a test key generator, which receives the hidden test key seed from randomly selected scan chains, and then generates a unique key for each test pattern. An authentication module is also introduced to verify the validity of the test patterns. Through key verification, if a test vector contains valid key seed, the design will perform normal scan operations. Conversely, if the seed hidden in a test vector cannot generate the expected test key, the scan output data will be scrambled by the random PUF responses, thereby effectively preventing attackers from inferring sensitive information. Theoretical analysis and experimental results show that the proposed secure DFT protects the cryptographic chip from all known scan-based side-channel attacks, while requiring no additional test preparation time and incurring only negligible low area overhead.