A Thyristor Random Access Memory with Localized Partial Insulator Structure to Improve Retention Characteristics at High Temperatures

Abstract Thyristor RAM (TRAM) is a promising alternative to capacitor-less one transistor (1T) Dynamic Random Access Memory (DRAM) due to its high-speed operation and the large current ratio between the programmed and unprogrammed memory states. However, its retention time is significantly reduced at high temperatures, limiting its reliability and performance in practical applications. This study introduces a localized partial insulator (LPI) structure to enhance the performance of silicon-based 2-terminal TRAM (2-T TRAM) under high-temperature conditions. The LPI structure minimizes junction leakage, effectively retaining excess carriers in the p-base region. Simulation results using Synopsys Sentaurus TCAD show that the optimized LPI structure improves retention time by 69.07 % at 400 K, reaching 3.28 ms. Moreover, the 1-cycle energy consumption is reduced by 11.47 %, enhancing energy efficiency. Additionally, an asymmetric LPI design further reduces the required voltage application time for memory operation by 21.34 %, shortening it to 5.5 ns. Our proposed design ensures faster and more stable operation without compromising retention or reliability. The results demonstrate that the proposed LPI structure effectively addresses high-temperature challenges, enhancing retention time, energy efficiency, and operation speed. This study highlights the LPI structure as a practical solution for developing high-performance, energy-efficient, and reliable next-generation 1T DRAM technologies.