FPGA implementation of high throughput encoder and decoder design of lossless canonical Huffman machine

This research presents the transfer of multibit symbol characters and large data symbols, which pose challenges in data transfer and reception due to complexity and memory constraints. Traditional compression and decompression schemes suffer from data loss, low throughput, and high encoding time. To address these issues, we introduce a modern hardware architecture based on the Canonical Huffman encoding and decoding computation method, integrated with frequency counting, sorting, state machine optimization, and barrel shifter techniques. This reconfigurable hardware accelerator minimizes memory storage requirements and utilizes fewer hardware resources. The Canonical Huffman encoder and decoder efficiently handle the multibit characteristics of data compression, significantly reducing memory usage and processing time. The proposed approach processes 160-bit input data, generating a compressed output of 90 bits using variable-length Canonical Huffman codes. The optimized hardware implementation has been verified for lossless compression and decompression using Xilinx 14.7 and ModelSim, with FPGA implementation on the Virtex-5. The improved VLSI system configuration using the Canonical Huffman method achieves a throughput of 144 GB/s for the encoder and 991 GB/s for the decoder, with an improved compression ratio of 56.27%. • High-throughput encoder and decoder design for canonical Huffman coding. • FPGA-based implementation ensures speed and hardware efficiency. • Supports lossless compression for real-time data applications. • Optimized architecture reduces latency and resource usage. • Achieves up to 144–991 GB/s throughput, 3.30 mW leakage power, and 56.26% better compression.