Effects of parasitic inductances in series-parallel topology with SiC MOFETs applied to a buck converter

The increasing use of Silicon Carbide (SiC) MOSFETs in high-power applications has presented challenges in parallel and series connections due to parasitic elements, such as inductances and capacitances. These elements can lead to imbalances in current and voltage distribution, as well as current spikes and overvoltages, which negatively impact device efficiency. In parallel configurations, parasitic inductances cause non-uniform current distribution, while in series configurations, they result in uneven voltage division. Unfortunately, the issue of unbalanced parasitic elements in series or parallel devices has been poorly documented in the literature. Despite the adverse effects of unbalanced parasitic elements in power converters, less interest has been devoted to them in the literature. Therefore, it remains unclear how parasitic unbalanced elements affect the voltage and current balance of SiC MOSFET devices when they are connected in series-parallel topologies. The main objective of this work is to analyze the effects of unbalanced parasitic inductance in series-parallel SiC MOSFETs on the drain current, drain-source voltage, and device losses during the switching and conduction states. The study uses a 450 W buck converter configured with three SiC MOSFETs, two connected in parallel with one in series. The buck converter is implemented with a duty cycle of 50%. The experimental results indicate that an unbalanced parasitic inductance in the electronic circuit generates voltage discrepancies of up to % during transient off states and 16% during on states in series and parallel devices. Additionally, the slopes of the on and off transients are reduced, leading to increased current rise and fall times through the drain. One proposed solution to enhance the switching characteristics of SiC MOSFETs is reducing the gate resistance, which results in a 49.6% reduction in the rise time and a 45.1% reduction in the fall time of the current through the drain. • Effect of parasitic inductances in series-parallel configurations of SiC MOSFETs. • Quantitative analysis of how parasitic inductances impact switching losses and transient characteristics (rise/fall times)