An energy and cost-effective realization of high-performance single-layer vedic multiplier in quantum-dot cellular automata

Abstract Quantum-dot cellular automata (QCA) is a promising nanotechnology offering numerous advantages over traditional transistor-dependent technology, featuring lower energy requirements and faster operation. This work delves into developing an optimized QCA-based 2-bit Vedic multiplier essential in arithmetic operations. The suggested multiplier is designed using cell interaction-based fault-tolerant half-adder circuit and majority gates within a co-planar architecture. An extensive defect analysis underscores the half-adder circuit’s resilience for larger circuits. The suggested design is comprehensively evaluated using the QCADesigner-E and QCAPro software on several design parameters, such as area, quantum cost, complexity and energy dissipation. Furthermore, the impact of temperature on output polarization is thoroughly examined. The simulation results revealed remarkable improvements in several key circuit metrics. The proposed 2-bit multiplier exhibits a notable 46.2% decrease in latency and a remarkable 90.7% reduction in quantum cost, with reduced crossovers compared to the closest reported design. The suggested 4-bit Vedic multiplier also outperforms several existing QCA-based multipliers, offering a highly efficient and compact design. These significant enhancements are attributed to the optimized cell-interaction mechanism in QCA technology, showcasing its potential for efficient and high-performance circuit design, as underscored in this research’s findings. The superior metrics and reduced fabrication complexity of the suggested multiplier facilitate its practical implementation in various nanoelectronics applications.