Challenges and responses of metrology technologies for the new wave of 3d NAND devices

Recent advancements in semiconductor devices are driven by the growing demand for massive computing power and high memory density in high-performance computing (HPC) and AI applications. Achieving this requires high-speed signal transmission through dense interconnects between chips and systems, leading to the adoption of 3D architectures to enhance energy efficiency in the AI era. In particular, 3D NAND heavily relies on the Hybrid Copper Bonding (HCB) process to integrate the CMOS periphery wafer with the memory array wafer, introducing new process control challenges. To address these, we identified key monitoring steps and critical monitoring parameters within HCB processes. Additionally, we categorized wafer geometry considerations into two main areas: wafer inner space and wafer outer space. This paper explores metrology challenges and potential solutions, aligning with industry requirements at key monitoring steps in both wafer inner and outer space areas.