Guarding-Based C-V Characterization of 10 kV SiC MOSFET in Half-bridge Module Configuration

Capacitance-Voltage (C-V) characteristics of SiC MOSFETs are critical for understanding their dynamic performance. Direct C-V measurement on a 10 kV SiC MOSFET die is hindered by insulation challenges, necessitating the use of a specialized fixture. As an alternative, measurements through a half-bridge power module offer a feasible solution. However, parasitic capacitances within the power module, comparable in magnitude to the intrinsic capacitances of 10 kV SiC MOSFETs, can affect measurement accuracy. This paper proposes a guarding-based method and an analytical approach to characterize MOSFET capacitances in a power module configuration, enabling precise separation of intrinsic MOSFET capacitances from parasitic effects. A comprehensive comparison of the two methods is presented using C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</inf> - V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> measurements for a 10 kV SiC MOSFET as a case study. Based on the experimental verifications, the proposed guarding-based method is accurate, straightforward and feasible.