Impact of Gate Resistor Configurations on Current Balancing in Paralleled SiC MOSFETs

To ensure availability and larger 2nd sourcing capabilities, paralleling discrete SiC MOSFETs is becoming more popular as the application's current requirements are increasing rapidly. However, the dynamic and static drain currents need to be well balanced when driving SiC MOSFETs in parallel in order to ensure power loss balancing. Apart from the device characteristics and the power circuit layout, the gate driver circuits also play a significant role, especially when dealing with high slew rates during switching. In this work, the switching behavior of paralleled discrete SiC MOSFETs are evaluated with different gate resistor configurations under various mismatch conditions. The switching loss imbalance and oscillations are analyzed for each case. In the end, based on the measurement and analysis results, a design principle is proposed to determine the optimal gate resistor configuration to drive paralleled devices.