400V SiC in Next-Generation 3-Level Flying Capacitor Bridgeless Totem-pole PFC

This paper proposes the design and implementation of a 3-level flying capacitor bridgeless totem-pole power factor correction (3L-FC-BTP-PFC) converter utilizing recently launched 400V Silicon Carbide (SiC) devices. It outlines key considerations and design challenges associated with adopting 400V SiC devices in place of a low-voltage series-connected silicon (Si) MOSFET arrangement. The proposed topology combines the benefits of a bridgeless totem-pole arrangement with the advantages of SiC technology. This combination enables superior performance in terms of higher efficiency, reduced gate driver complexity, increased system robustness, and enhanced power density. A comprehensive overview of the converter's operation, gate driver design, proposed power stage architecture, along with corresponding real-world experimental test results is presented.

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Publication Details

Published
2025-03-16
DOI
https://doi.org/10.1109/apec48143.2025.10977447
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

400V SiC in Next-Generation 3-Level Flying Capacitor Bridgeless Totem-pole PFC

Rytis Beinarys, Séamus O’Driscoll
Silicon Carbide Semiconductor Technologies
article

400V SiC in Next-Generation 3-Level Flying Capacitor Bridgeless Totem-pole PFC

Rytis Beinarys, Séamus O’Driscoll
article en

Abstract

This paper proposes the design and implementation of a 3-level flying capacitor bridgeless totem-pole power factor correction (3L-FC-BTP-PFC) converter utilizing recently launched 400V Silicon Carbide (SiC) devices. It outlines key considerations and design challenges associated with adopting 400V SiC devices in place of a low-voltage series-connected silicon (Si) MOSFET arrangement. The proposed topology combines the benefits of a bridgeless totem-pole arrangement with the advantages of SiC technology. This combination enables superior performance in terms of higher efficiency, reduced gate driver complexity, increased system robustness, and enhanced power density. A comprehensive overview of the converter's operation, gate driver design, proposed power stage architecture, along with corresponding real-world experimental test results is presented.

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