Numerical Analysis and Optimization of Chip-Level Drop Impact Reliability for Chiplet Based on Si Interposer

Chiplet technology has become a hotspot in the post-Moore era and widely used in portable electronic products. However, the compact and complex internal structure of Chiplet packaging may seriously degrade the drop reliability. In this work, the drop reliability of Chiplet is analyzed, modeled, simulated, quantitatively predicted and optimized. A variety of Chiplet quarter models is established, and the distribution of deformation and stress is analyzed using the finite element method, revealing that the Si interposer is a critical location. Predictions are made for more complex multi-layer stacking structures, and fitting curves are obtained to achieve rapid drop reliability prediction. The impact of Si interposer thickness on the reliability of critical location during impact is investigated, showing that a thicker Si interposer can improve reliability. Based on these findings, a structural design method is proposed to significantly enhance Chiplet reliability, reducing deformation at critical location by 98.4% and maximum stress on the Si interposer by 39.9%.