Hardware Implementation of Virtual Resistance Based FRT Logic in Programmable 3-Level ANPC Inverters

This paper develops a hardware testbed to experimentally validate a virtual resistance-based fault ride-through (FRT) and current limiter logic for a grid-forming inverter (GFM). The testbed consists of three-level ANPC (active neutral point clamped) programmable inverters and a power circuit representing a transmission system equivalent. The paper presents the implementation details and sample experimental results. Firstly, the FRT logic with necessary GFM control are designed and simulated in MATLAB/Simulink software. Then, the inverter microcontrollers are programmed for the hardware test. Two GFM inverters are synchronized in parallel at the beginning of the experiment. Then, various balanced and unbalanced faults experiments are performed with the test system. A programmable relay is used to capture high resolution data during fault. The voltage and current sensor measurements of inverters are recorded and logged in real-time. Finally, the results from hardware and simulation are compared to justify the consistency of the hardware implementation with simulation.