Online Detection and Reduction of the Influence of Parameter Tolerance of Paralleled SiC MOSFETs in an EV Inverter Environment

The tolerance of SiC MOSFET parameters like threshold voltage, parasitic capacitances, and transconductance can cause large switching loss tolerances and asymmetrical current sharing in a power module. Online detection of dispersion of these parameters facilitates driving strategies that mitigate the effect of these large tolerances. A technique based on a simple slow rising gate-source voltage waveform at inverter no-load condition is used to detect the tolerances of the threshold voltage and input capacitance of the paralleled SiC MOSFETs. The detected parameters show an excellent correlation with measurements performed with a curve tracer under various operating conditions. The tolerances of the parameters detected online are used to derive a novel pre-defined driving strategy that reduces switching loss tolerance in paralleled SiC MOSFETs during an electric vehicle (EV) inverter’s operation. The strategy is realized with a novel active voltage-source gate driver (AVSGD) having configurable gate resistances and delays. Double pulse test (DPT) results with the driving strategy show an improved current sharing and turn-on switching loss symmetry between the paralleled SiC MOSFETs.