Layout Optimization for Parasitic Inductance Reduction of GaN-based NPL.X Multilevel Inverter

The increasing adoption of gallium nitride (GaN) devices has raised the bar for layout optimization techniques to achieve lower parasitic inductance design. This is driven by the high dv/dt characteristics of GaN devices, which make them particularly sensitive to parasitic inductances. This challenge is especially prominent in multilevel inverters (MLIs), where the neutral point connection complicates PCB layout and busbar design with low parasitic inductance. The newly proposed neutral-point-less X-type (NPL.X) MLI topology eliminates the neutral point connection, simplifying layout optimization. However, its complex structure can lead to poor switch placement, introducing undesirable parasitic elements and causing voltage overshoots. This paper proposes a novel circuit configuration for the NPL.X topology to reduce parasitic inductance from inefficient switch placement. The optimized configuration expected to significantly lowers commutation loop inductance, mitigating voltage overshoots. To validate the capability of the new configuration, a PCB layout based on the proposed configuration is analyzed, showing a 60% reduction in loop inductance. Simulation results, using extracted parasitic inductances from the PCB, show up to a 75% reduction in voltage overshoots across switches and up to 90% across diodes under varying load and dv/dt conditions. These results highlight the potential of the new configuration to enhance the performance and reliability of the GaN-based NPL.X.