DC-Link Capacitor Board Design for Low Parasitic Inductance

DC-link capacitors absorb ripple current and provide stable DC voltage in power converter applications. As switching speed and frequency increase, the parasitic inductance of the DC-link capacitor causes transient overvoltage, which can lead to premature failures of the semiconductor and capacitor. Therefore, the parasitic inductance of the DC-link board should be minimized to increase the resonance frequency above the switching frequency. This paper explores the effects of parasitic inductance on the capacitor voltage and explores three different DC-link board layouts to determine the best configuration for decreased parasitic inductance. The board designs explored the presence of a bottom layer of copper and the alignment of adjacent capacitors. FEM simulation was used with varying numbers of parallel capacitors. It was found that increasing the number of capacitors will cause an initial decrease in parasitic inductance, then begin increasing. With an increased number of capacitors in parallel, the presence of a copper bottom layer with direct parallel capacitors allowed for a 50% decrease in parasitic inductance, and interleaving parallel capacitors offered an overall 93% decrease in parasitic inductance. Experimental results were conducted to validate that the interleaving of parallel capacitors allows for additional reduction in parasitic inductance, which showed a 59% decrease in parasitic inductance from direct parallel oriented capacitors and a 77% increase in resonant frequency.