Circulating Current Control with Loss Reduction for Parallel Connected Inverters
Connecting inverters in parallel is a common method for increasing current capacity. Due to the difference in the delay time and on-voltage of the gate circuit and the switching element between the parallel inverters, a circulating current is generated between the inverters connected in parallel. In this paper, we propose a method to suppress the circulating current of a parallel inverter and to reduce the loss. By adjusting the turn-on and turn-off timing, the voltage difference between the inverters is reduced. As a result, the circulation current is suppressed. The effect of the proposed method of adjusting the turn-on delay time by matching the turn-off delay time was experimentally verified. By adjusting the turn-on and turn-off timing, the voltage difference between the inverters is eliminated, the circulating current is suppressed, and the current imbalance rate is less than 1%. It was experimentally verified that increasing the turn-on delay time difference from 39 ns to 76 ns and narrowing the turn-off delay time difference from 43 ns to 3 ns could reduce total switching losses by 3.5%.
Authors
- Naoto Onuma
- Shun Endo
- Yuichi Mabuchi
- Nobuyuki Takayama (ORCID: https://orcid.org/0000-0001-9418-9657)
- Masato Ando (ORCID: https://orcid.org/0000-0002-0125-9714)
- Yohei Matsumoto
- Takae Shimada
- Masaki Miyamae
Institutions
- Hitachi (Japan) (JP)
Publication Details
- Published
- 2025-03-16
- DOI
- https://doi.org/10.1109/apec48143.2025.10977493
- Primary Topic
- Multilevel Inverters and Converters
- Type
- article
- Field-Weighted Citation Impact
- 0.00