Improving Dynamic Current Sharing between Parallel MOSFETs by Optimizing Device Parameters

In today’s applications, there is a persistent demand for higher power capabilities, where a single MOSFET is insufficient to meet the required power needs in applications such as Light Electric Vehicles (LEVs), e-scooters, e-forklifts, etc. To address this, designers often employ multiple MOSFETs in parallel to share the currents. However, paralleling of MOS-FETs can lead to dynamic and steady state current imbalance issues, primarily caused by two factors: layout asymmetries and unmatched MOSFET parameters. These imbalances will result in uneven power dissipation among the paralleled MOSFETs, which can compromise the system’s overall performance and reliability. Semiconductor manufacturers are actively addressing this challenge through the development of new technologies that are designed to facilitate parallel operation and provide improved performance and reliability. This paper will demonstrate a comprehensive comparison of dynamic current sharing between parallel MOSFETs during hard switching events, and the impact of different MOSFET parameters such as gate-source threshold voltage window and transconductance on it. It will also provide designers step by step guidance on emulating different gate-source threshold voltages for evaluating dynamic current sharing, which will help them choose the best MOSFETs for their target applications.