Coaxially Nested 3.3 kV SiC MOSFET Packages with Uniform Interpackage Electric Field Distribution

This work proposes a power semiconductor package architecture that scales well with voltage while simultaneously limiting commutation loop inductance and promoting good current balance between parallel devices. The target application is a coaxial power electronics conversion system which inherits the power density and voltage scaling benefits of a high voltage cable. This architecture is composed of a pair of coaxially nested single switch packages with similar internal structures and fabrication procedures. Aided by their coaxial commutation loop, the 3.3 kV SiC MOSFET single switch packages have a combined contribution to the commutation loop inductance of just 2.8 nH at 100 kHz in simulation. Static characteristics of the packages are comparable to bare die specifications from the datasheet and dynamic characterization demonstrates the impact of the low commutation loop inductance achieved with this structure. Using a prototype of the system’s thermal management solution, the measured junction-to-case thermal resistance was found to be 0.073 °C/W for the input switch.