Heterogeneous Hardware Architecture with Linear Algebra Acceleration

Linear algebra is essential in machine learning for dealing with large datasets. Linear algebra acceleration is directly related to the hardware used. Many works have proposed linear algebra accelerator architectures with the goal of improving energy efficiency and speed. The characterization of trade-offs in balancing acceleration and programmability of software routines is still insufficiently explored, particularly for edge analytics. Therefore, this paper proposes a heterogeneous hardware architecture consisting of a RISC-V system-on-chip and a linear algebra accelerator. Tested on Efinix Trion T120BGA324, the new architecture incorporates software routines and is clocked at 50 MHz. The improved design provides better timing closure and lower logic element use, with the lowest slack being 2.102 ns and the highest logic element use being 66.40%. The design incorporates a software routine for improved data management, reduced hardware resource utilization, and some computational load. The results show that the heterogeneous architecture outperforms the RISC-V System-on-Chip standalone by 156× in General Matrix Multiplication without accuracy loss.