Study of Layout Parasitic Elements Impact on Characteristics of Precision Ultra-High Frequency Integrated Circuits

In this paper, we examine the layout parasitic elements impact on the static and dynamic characteristics of integrated circuits, in particular analog-to-digital and digital-to-analog converters. Using the most common technological parameters for 180 nm CMOS technology, we carried out a theoretical assessment of the MOSFET intrinsic parasitic resistances and capacitances. We compared the potential influence of MOSFET's intrinsic parasitic elements and layout parasitic elements on the converters characteristics. Using computer-aided design software, we simulated the performance of a 14-bit digital-to-analog converter with a 1 GHz conversion frequency with and without layout parasitic elements. Layout parasitic resistances changed the most significant bit output current level by 113 μA and increased the temperature coefficient by more than five times from 4.8 to 23.6 ppm/°C Parasitic resistances and capacitances jointly increased the signal settling time from 0.8 ns to 2.5 ns and thereby reduced the con-version frequency by more than three times from 1250 to 400 MHz. We concluded that when designing such precision ultra-high frequency integrated circuits as digital-to-analog or analog-to-digital converters, a procedure for reducing the influence of layout parasitic elements is necessary.