High-Speed-Recognition Artificial Intelligence Chip Based on ARM+FPGA Platform

We developed a license plate recognition platform based on the Zynq-7000 SoC. A field-programmable gate array (FPGA) was used to build a low-power, high-speed neural network. The system leveraged the ARM processor for initial image processing and used standard license plate characters as a training dataset. After filtering and processing, the images were resized to 28 × 28 pixels in the grayscale format and then transmitted to the FPGA for high-speed recognition. The digital circuit in the FPGA was implemented using Verilog in a deep learning neural network architecture, with the neurons configured as (57, 12, 57, 36) in a hidden layer. The model was trained for 60 epochs. The neural network was also trained with a dataset consisting of 26 English alphabet characters and 10 digits, augmented using image dilation and erosion. Recognition accuracy was 83.33%. Using Vivado, the system was successfully deployed on the Zynq-7000 SoC, demonstrating its potential in intelligent applications.

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Publication Details

Published
2025-04-29
DOI
https://doi.org/10.3390/engproc2025092033
Citations
3
Primary Topic
Advanced Algorithms and Applications
Type
article
Field-Weighted Citation Impact
3.64
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article

High-Speed-Recognition Artificial Intelligence Chip Based on ARM+FPGA Platform

Shu‐Jung Chen, Yu-Hsien Wu, Chin-Hsiung Shen, Chia-Lun Yu
3 citations
Advanced Algorithms and Applications
3.64
article

High-Speed-Recognition Artificial Intelligence Chip Based on ARM+FPGA Platform

Shu‐Jung Chen, Yu-Hsien Wu, Chin-Hsiung Shen, Chia-Lun Yu
article en
3 citations

Abstract

We developed a license plate recognition platform based on the Zynq-7000 SoC. A field-programmable gate array (FPGA) was used to build a low-power, high-speed neural network. The system leveraged the ARM processor for initial image processing and used standard license plate characters as a training dataset. After filtering and processing, the images were resized to 28 × 28 pixels in the grayscale format and then transmitted to the FPGA for high-speed recognition. The digital circuit in the FPGA was implemented using Verilog in a deep learning neural network architecture, with the neurons configured as (57, 12, 57, 36) in a hidden layer. The model was trained for 60 epochs. The neural network was also trained with a dataset consisting of 26 English alphabet characters and 10 digits, augmented using image dilation and erosion. Recognition accuracy was 83.33%. Using Vivado, the system was successfully deployed on the Zynq-7000 SoC, demonstrating its potential in intelligent applications.

National Changhua University of Education (TW)
Openalex Percentile: Top 8%
Advanced Algorithms and Applications
3.64
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