Teaching Digital Logic Design Using a Floating-Point Processor

This paper presents a framework for teaching digital logic design using a 32-bit floating-point processor, developed as part of Kartikey Sharan's master's thesis.The project leverages SystemVerilog and the IEEE 754 standard to provide hands-on experience with floating-point arithmetic, FPGA implementation, and digital system design.Integrated into advanced digital logic courses at the University of Texas at Arlington, the project offers practical exposure through FPGA platforms like ModelSim and Terasic's DE10-Lite board.Students learn digital logic principles, hardware interfacing, and real-world engineering skills through this interactive, application-driven approach.