Design and Implementation of Lightweight Neural Network Inference Accelerator Based on FPGA

This study focuses on the design and optimization of lightweight neural network inference accelerator based on FPGA, and proposes an efficient accelerator architecture suitable for resource-constrained scenarios. The performance of the design under various configurations is verified by testing and analyzing different network models (such as MobileNetV2, SqueezeNet, ResNet-18) and computational accuracy. Experimental results show that the FPGA accelerator designed in this paper achieves a good balance between throughput, latency and power consumption, and can meet the needs of lightweight neural network inference tasks, especially in the low-precision configuration of 8-bit fixed-point numbers. Significant energy efficiency improvement is achieved. Complex models such as ResNet-18 show their adaptability at high throughput, while lightweight models such as MobileNetV2 excel in low latency and low power consumption. Through reasonable architecture optimization, this paper demonstrates the great potential of FPGA accelerators in deep learning inference, and provides an effective hardware solution for efficient inference in applications such as smart IoT and edge computing.