Research on Synchronization Problem of Triple Redundancy Flight Control Computer

This paper introduces an integral data balancing algorithm using dual-port RAM as the hardware medium. Its aim is to address the issue of inconsistent integral data between master and slave controls due to clock errors in the operation of a three-redundant flight control computer. We first propose a three-redundant flight control computer architecture based on comparative monitoring, and we design the software and hardware to support subsequent semi-physical simulations. The data balancing algorithm primarily targets integral data by exchanging the integrator output values among the three main branches to achieve signal balance. The monitoring branch then transmits the balanced integral values to the main branch, ensuring consistency between the master and slave controls. Simulation verification demonstrates that this data balancing algorithm effectively resolves the issue of inconsistent integral data under both synchronous and asynchronous conditions, thereby enhancing the reliability of the flight control computer.