Error Detection and Correction Codes for Memories with Enhanced Detection Abilities

Recent memories in different processors suffer from increasing threats of errors. Error correction and detection codes with higher detection abilities are required. This work presents the design and implement of error control abilities of codes in different data lengths, realizing burst error correction abilities from 1 bit to 4 bits, detection abilities of 3-bit random errors and detection abilities of over 5 bits burst errors. Lower hardware overhead is realized for error detection. The proposed codes can be adopted to improve reliability of memories when increasing bits of burst errors and random errors need correcting and recovering.