Implementation of a Faster B+ Tree*

In our paper, we have tried to implement some enhancements to the B+ tree structure with the aim to improve its performance and throughput. Our focus is on improving the performance of B+ tree on SIMD architecture machines. By referencing prior research, we identified significant gaps between traditional B+ tree implementations and the capabilities of SIMD architectures, and we have tried to implement some solutions to overcome those gaps. These gaps primarily stem from the mismatch in how data is processed and accessed between the two paradigms. Traditional B+ trees are optimized for sequential data access patterns, whereas SIMD architectures excel in parallel data processing. We have tried to identify the disparities and implement some solutions to overcome them. Our approach aims to mitigate the adverse effects of these gaps, thereby enhancing the B+ tree's efficiency in modern computing environments. Through empirical evaluation and comparative analysis, we demonstrate the potential improvements in performance and throughput achievable with these modifications.