Optimizing Cache Management Policy for Fast Packet Processing in NFV Data Plane

Establishing efficient caching in the data plane is crucial for the performance of packet forwarding for network function virtualization(NFV). For switches that provide network functions such as forwarding, routing, and firewall, the on-chip memory in the data plane is closest to the packet processing logic. However, due to hardware constraints or limitations in the programming model, the programmability and memory access capabilities of data plane caching in many network devices, such as programmable switches, smart network cards, and DPUs, are often restricted. As a result, most existing data plane caches rely on simple and inefficient replacement strategies. In this paper, an analysis of the limitations in programmability of the data plane is conducted, and an algorithm with bit-slice operators is proposed to determine the update and eviction strategy for each item in the cache array. Leveraging the principles of limited associativity design, the storage structure of the ternary match kind identifier (TCAM) table is optimized due to constraints on the number of mask bits. Efficient utilization of cache hits is achieved by setting timestamps and packet flow identifiers in registers. Experimental results demonstrate that our caching strategy exhibits significant improvements in hit rate and latency performance compared to some previously proposed approaches.