Investigating the Performance of Sub-10-nm WSi₂N₄ MOSFETs With Native Dielectric Through a Machine Learning Tight-Binding Framework

Monolayer WSi<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> has emerged as a promising 2-D semiconductor for high-performance ultrascaled MOSFETs. In this work, we use machine learning techniques to generate a sparse tight-binding (TB) Hamiltonian and evaluate the performance of sub-10-nm n-type and p-type WSi<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> MOSFETs with native Si<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> as the gate dielectric. To validate our approach, we compare the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i>–<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics generated by our machine learning TB (MLTB) model with those obtained from a TB model using the maximally localized Wannier function (MLWF) approach for a monolayer HfS<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> MOSFET, demonstrating excellent agreement. Our results show that both n-type and p-type WSi<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> MOSFETs meet the International Roadmap for Devices and Systems (IRDS) 2022 ON-current (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub>) target for high-performance (HP) applications at channel lengths (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>ch</roman></sub>) of 5–10 nm. For high-density (HD) applications, n-type and p-type devices can be scaled down to 7 and 8 nm, respectively, while maintaining IRDS compliance. At a 10-nm channel length, n-type devices achieve a higher <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub> than p-type devices, while both exhibit comparable subthreshold swing (SS) close to the 60-mV/dec limit at room temperature. However, as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>ch</roman></sub> decreases, n-type devices experience greater SS degradation than p-type devices due to enhanced source-to-drain tunneling, allowing p-type devices to outperform at shorter channel lengths. In addition, transport simulations reveal directionally isotropic carrier behaviors in WSi<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub>. These findings underline the potential of WSi<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> for next-generation ultrascaled transistors and showcase the utility of machine-learning-based approaches in modeling devices constructed with novel 2-D materials.