Clock Edge Triggering Control in Topology-Based Logic Dynamic Systems Using Matrix Approaches
In this brief, we depict the clock edge triggering control of topology-based logic dynamic systems (TLDSs) often seen in nowadays digital circuits and electronics chips. The state-space equations (SSEs) of TLDSs are firstly derived, and the necessary and sufficient conditions are given for determining the existence of a clock edge triggering control in TLDSs using the properties of the matrices in the SSEs. The effectiveness of the proposed method is then validated in the equivalent TLDS of a practical engineering chip.
Authors
- Yingzhe Jia (ORCID: https://orcid.org/0000-0001-5638-8890)
- Qianming Xu (ORCID: https://orcid.org/0000-0002-6188-2508)
- Abdelhamid Tayebi (ORCID: https://orcid.org/0000-0002-9049-4651)
- Peng Guo (ORCID: https://orcid.org/0000-0002-0684-0671)
- Jiayu Hu (ORCID: https://orcid.org/0000-0003-0614-5895)
- An Luo (ORCID: https://orcid.org/0009-0007-8563-414X)
- Yiliang Li
Institutions
- Shandong University (CN)
- Hunan University (CN)
- Lakehead University (CA)
Publication Details
- Journal
- IEEE Transactions on Circuits & Systems II Express Briefs
- Published
- 2025-04-29
- DOI
- https://doi.org/10.1109/tcsii.2025.3565551
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Natural Science Foundation of Shandong Province