A 247–272-GHz SiGe Frequency Doubler With 8.2-dBm <i>P</i> _sat Enhanced by Optimized Fundamental Load Impedance and Hybrid-Mode Driver Amplifier

This article presents the analysis, design, and implementation of an integrated sub-THz frequency doubler. Using the VBIC model of the heterojunction bipolar transistor (HBT), we optimize the intrinsic base-emitter and collector-emitter voltage waveforms to maximize the second harmonic output power and further derive the optimal external input power sources and load terminals. We demonstrate that maximizing the second harmonic output power requires a purely capacitive fundamental load impedance. Furthermore, our analysis shows that applying optimal second harmonic input power can further enhance the second harmonic output power. To validate the theory, a frequency doubler is designed and fabricated using a 130-nm SiGe process. The doubler consists of a common-emitter push-push doubler core with an optimized fundamental load impedance, and a hybrid-mode driver amplifier to deliver both the fundamental and second harmonic input powers. The fabricated doubler chip exhibits a measured maximum saturated output power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {{P}_{\textbf {sat}}}$</tex-math> </inline-formula>) of 8.2 dBm, with a measured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {{P}_{\textbf {sat}}}~3$</tex-math> </inline-formula>-dB bandwidth ranging from 247 to 272 GHz. Compared with state-of-the-art doublers using the same SiGe process, the proposed doubler achieves the highest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {{P}_{\textbf {sat}}}$</tex-math> </inline-formula> per unit emitter area and demonstrates a 1.6-fold improvement.