The Implementation of the Physical Unclonable Function in a Field-Programmable Gate Array for Enhancing Hardware Security

The integrated circuit (IC) industry has rapidly developed, with chip hardware security assuming a critical role in IC design. The physical unclonable function (PUF) exploits semiconductor process variation differences to generate unique responses randomly. Due to its non-replicability, PUF has emerged as one of the most commonly employed methods in hardware security. We propose PUF implementation employing an automatic scan selector to toggle between eight sets of multiplexers. With an 8-bit selector, 256 state inputs are automatically generated, and the PUF architecture enables a 256-bit unique identification code for the chip. Finally, the generated identification code is outputted either serially or in parallel and implemented on a field-programmable gate array platform.

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Publication Details

Published
2025-04-27
DOI
https://doi.org/10.3390/engproc2025092023
Primary Topic
Physical Unclonable Functions (PUFs) and Hardware Security
Type
article
Field-Weighted Citation Impact
0.00

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article

The Implementation of the Physical Unclonable Function in a Field-Programmable Gate Array for Enhancing Hardware Security

Kuang-Hao Lin, I-Chen Wang, Weihao Wang
Physical Unclonable Functions (PUFs) and Hardware Security
article

The Implementation of the Physical Unclonable Function in a Field-Programmable Gate Array for Enhancing Hardware Security

Kuang-Hao Lin, I-Chen Wang, Weihao Wang
article en

Abstract

The integrated circuit (IC) industry has rapidly developed, with chip hardware security assuming a critical role in IC design. The physical unclonable function (PUF) exploits semiconductor process variation differences to generate unique responses randomly. Due to its non-replicability, PUF has emerged as one of the most commonly employed methods in hardware security. We propose PUF implementation employing an automatic scan selector to toggle between eight sets of multiplexers. With an 8-bit selector, 256 state inputs are automatically generated, and the PUF architecture enables a 256-bit unique identification code for the chip. Finally, the generated identification code is outputted either serially or in parallel and implemented on a field-programmable gate array platform.

National Formosa University (TW)
Thailand Science Research and Innovation, National Science and Technology Council
Openalex Percentile: Top 93%
Physical Unclonable Functions (PUFs) and Hardware Security
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