Domino Logic Approach for 8-bit Comparator Design

Digital comparators are widely used in digital systems for tasks requiring data comparison. Conventional comparators designed using technologies such as CMOS provide the necessary speed and accuracy required by comparator applications. However, these comparators often face limitations and trade-offs between speed and power efficiency, especially in high-frequency applications due to their complex static design. This results in higher energy consumption and reduced operational efficiency, especially in low-power and high-frequency environments. To address these limitations, this paper explores a domino CMOS logic approach to design an 8-bit comparator that reduces power consumption. This project aims to provide an alternative to conventional CMOS comparators in high-performance VLSI circuits.