Hardware-Accelerated Non-Contact System for Sleep Disorder Monitoring and Analysis

This study analyzes human sleep disorders using non-contact approaches. The proposed approach analyzes periodic limb movement disorder (PLMD) under sleep conditions. This was conceptualized as data capture using a non-contact approach with ultrasonic sensors. The model was designed to estimate PLMD and classify it using real-time sleep data and a machine learning-based random forest classifier. Hardware schemes play a vital role in capturing sleep data in real time using ultrasonic sensors. A field-programmable gate array (FPGA)-based accelerator for a random forest classifier was designed to analyze PLMD. This is a novel approach that aids subjects in taking further medications. Verilog HDL was used for PLMD estimation using a Xilinx Vivado 2021.1 simulation and synthesis. The proposed method was validated using a Xilinx Zynq-7000 Zed board XC7Z020-CLG484.

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Publication Details

Journal
Sensors
Published
2025-04-26
DOI
https://doi.org/10.3390/s25092747
Citations
1
Primary Topic
Restless Legs Syndrome Research
Type
article
Field-Weighted Citation Impact
1.35
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Hardware-Accelerated Non-Contact System for Sleep Disorder Monitoring and Analysis

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Hardware-Accelerated Non-Contact System for Sleep Disorder Monitoring and Analysis

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article en
1 citations

Abstract

This study analyzes human sleep disorders using non-contact approaches. The proposed approach analyzes periodic limb movement disorder (PLMD) under sleep conditions. This was conceptualized as data capture using a non-contact approach with ultrasonic sensors. The model was designed to estimate PLMD and classify it using real-time sleep data and a machine learning-based random forest classifier. Hardware schemes play a vital role in capturing sleep data in real time using ultrasonic sensors. A field-programmable gate array (FPGA)-based accelerator for a random forest classifier was designed to analyze PLMD. This is a novel approach that aids subjects in taking further medications. Verilog HDL was used for PLMD estimation using a Xilinx Vivado 2021.1 simulation and synthesis. The proposed method was validated using a Xilinx Zynq-7000 Zed board XC7Z020-CLG484.

SensorsVol. 25(9)
Chaitanya Bharathi Institute of Technology (IN), Nanyang Technological University (SG), Koneru Lakshmaiah Education Foundation (IN)
Life in Land
Openalex Percentile: Top 20%
Restless Legs Syndrome Research
1.35
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