Design and Implementation of 32-bit Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol using Cadence

The Advanced Microcontroller Bus Architecture (AMBA), developed by ARM, is a widely adopted open standard that facilitates high-performance, low-power communication between functional blocks in System-on-Chip (SoC) designs. It enables modularity, scalability, and reusability in SoC development through a family of protocols including AHB (Advanced Highperformance Bus), AXI (Advanced extensible Interface), and APB (Advanced Peripheral Bus). Among these, APB is specifically designed for connecting simple, low-bandwidth peripherals such as UARTs, timers, and GPIOs due to its low complexity and reduced power consumption. This work presents the Design and Implementation of 32-bit AMBA APB Protocol using Cadence, showcasing a complete digital VLSI design flow. The project encompasses RTL coding in Verilog HDL, functional verification using testbenches, and synthesis using Cadence Genus to evaluate area, power, and delay reports. Following synthesis, the design undergoes placement and routing in Innovus, resulting in a GDSII layout generation. Post-synthesis and post-layout analyses are carried out to ensure that the design meets performance and physical constraints. The final GDS file confirms successful implementation from RTL to layout, making the protocol ready for silicon realization. This project demonstrates the integration of bus protocol design within a professional EDA environment, reflecting industry practices in hardware development and physical design