A Linearized Open-Loop MDAC with Memory Effect Compensation Technique for High-Speed Pipelined ADC Stage

This paper presents a prototype open-loop pipelined stage in a 45 nm CMOS process for supporting 1.8 GS/s and 10-bit design specifications of pipelined ADCs. In order to alleviate the severe non-linearity expressed by open-loop MDACs, an innovative current-mode harmonic compensation is proposed to provide input related third harmonic terms to cancel non-linearity. In addition, an effective double-sampling scheme is optimized by modifying compensation timing and input of a residual amplifier so that the pipelined stage can be immune to memory effect and improve power efficiency. The memory effect compensation scheme can provide a 21 dB improvement on output SNDR of the double-sampling pipelined stage. The simulation results illustrate that the open-loop pipelined ADC stage achieves an output SNDR of at least 52 dB with 840 mV input amplitude and 240 fF load while consuming only 11.24 mW.