A High Performance VLSI Architecture for the Computation of Markov Random Field Parameters

Image feature extraction is a crucial step for image segmentation in computer vision systems. Features used in image segmentation can be pixel-based or texture-based. Texture-based features have become widely used and reported in the literature; specifically, those that utilize Markov Random Fields (MRF). While the algorithmic development of such features has been documented, very little attention has been given to the development of dedicated hardware to compute MRF parameters, even though it is a computationally intensive task. This paper presents a new Very Large-Scale Integration (VLSI) architecture for the computation of MRF parameters. The proposed architecture can be part of a larger image segmentation system to aid in the segmentation of real-time high-quality video. To the author's knowledge, this is the very first dedicated architecture for computing MRF features suitable for image segmentation. The architecture has also been prototyped using a Xilinx FPGA development environment.